Since SystemVerilog can't x<=y (non-blocking assign) for x and y of class types I decided to try a giant always block and code my pipelines reverse order. Coping data using just = (blocking assign).
This would've been fine if each pipeline did not look at the data in the other pipelines. And as such get confused because the inline code changes some pipelines before the next gets a chance to look at the data.
After hours of research I found 2 things:
- a struct can be in x<=y; statement
- if you use the keyword automatic in your task/function declaration you can pass a struct/class by reference and avoid this cryptic error: "reference argument is illegal inside static task-function declaration".
That last would have been found faster if I'd remembered the keyword - but is very hard to find the opposite of static. Esp. since I didn't realize there was one.
Worse, there are hundreds of examples of SystemVerilog code that won't compile (at least with Cadence):
task xyz ( ref mytype_t a);should be
task automatic xyz (ref mytype_t a);
So now I've changed my data class into a struct, moved all the methods out to (automatic) tasks, and passed the struct in by reference. Now all my assignments are <= so I get pipelining for free - the way Verilog is supposed to be.
And it still doesn't work because.....
"Although it is not explicitly stated in the LRM, the Cadence implementation does not support the passing of a member of an array, or a member of a packed structure, by reference to a task or function."What is the point of having this c++ like OOP language if you can't pass pointers to array elements, or whole arrays, etc to a task/function? I'm at a loss.
Time to recode a bunch of stuff.